Synopsys Design Compiler Tutorial 2021 [exclusive] Official

Be careful using set_dont_touch on modules, as it prevents DC from optimizing across boundaries.

create_clock -name my_clk -period 10 [get_ports clk] set_input_delay 2.0 -clock my_clk [all_inputs] set_output_delay 1.5 -clock my_clk [all_outputs] Use code with caution. synopsys design compiler tutorial 2021

write -format verilog -hierarchy -output "my_design_netlist.v" write_sdc "my_design_final.sdc" Use code with caution. Pro-Tips for 2021 Synthesis: Be careful using set_dont_touch on modules, as it

Mastering Digital Synthesis: A Synopsys Design Compiler Tutorial (2021 Edition) Be careful using set_dont_touch on modules